The High-NA Revolution: How Intel Surpassed One Million Wafers and Reimagined the Future of Lithography

In a monumental achievement for the semiconductor industry, Intel has officially announced that its production facilities have successfully processed more than one million 300-mm wafers utilizing High-Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography tools. This milestone, reached in less than two and a half years since the assembly of its first scanner, marks a paradigm shift in how the world’s most advanced processors are manufactured. By achieving this scale, Intel has not only validated the viability of next-generation lithography but has effectively processed more High-NA wafers than the rest of the global semiconductor industry combined.

The Dawn of High-NA EUV: A Technical Overview

To understand the gravity of this milestone, one must first appreciate the physics of modern chipmaking. Traditional EUV lithography, which operates at a numerical aperture of 0.33, has been the backbone of leading-edge semiconductor manufacturing for several years. However, as the industry pushes toward angstrom-level process nodes, the limits of 0.33-NA become apparent.

High-NA EUV, with a numerical aperture of 0.55, represents a significant leap in resolution. By capturing a wider angle of light, these scanners can print smaller, more intricate features onto silicon, effectively enabling the next generation of power-efficient and high-performance computing. Intel’s early adoption of ASML’s Twinscan EXE:5000 and the newer, high-throughput EXE:5200B systems has positioned the company at the vanguard of this technological revolution.

A Chronology of Rapid Scaling

Intel’s journey toward the million-wafer mark has been defined by an aggressive integration schedule. The timeline of this achievement highlights a relentless pace of industrial adoption:

• Early 2022: The initial assembly and installation phase begins for Intel’s first High-NA EUV machines.
• Early 2024: Intel officially certifies the use of High-NA EUV scanners for its cutting-edge 18A process technology, signaling the transition from research and development to pilot production.
• February 2025: Intel reports a significant but nascent milestone of 30,000 wafers processed. At this stage, the focus was on process maturity, yield optimization, and machine calibration.
• September 2026: Intel confirms the million-wafer threshold. This rapid acceleration—from 30,000 to over one million in roughly 18 months—demonstrates the successful scaling of operational throughput and the maturation of the High-NA ecosystem within Intel’s fabs.

This trajectory is not merely a quantitative increase; it represents a fundamental mastery of a complex, high-risk manufacturing environment. By integrating these tools into the production flow of processors such as the Panther Lake series, Intel has successfully moved High-NA from the laboratory to the factory floor.

Supporting Data: Fleet Maturity and Throughput

The "million-wafer" figure is comprehensive, encompassing tool installation, certification, R&D, and actual production output. When placed in context with ASML’s own reports, the scale of Intel’s accomplishment becomes even more impressive.

Earlier this year, ASML disclosed that the global fleet of High-NA scanners—across all users—had processed approximately 500,000 wafers while maintaining an availability rate exceeding 80%. Given that Intel has now exceeded one million wafers, the company is responsible for the vast majority of the industry’s High-NA output. This dominance suggests that while other foundries may be exploring High-NA, Intel has achieved a level of process maturity and volume production that is currently unrivaled.

Furthermore, the addition of the EXE:5200B to the fleet—a tool engineered for higher throughput than its predecessors—has allowed Intel to accelerate its output despite the inherent challenges of high-resolution lithography.

The Challenge of Stitching: Why Size Matters

A critical hurdle in current High-NA lithography is the "stitching" problem. Due to the anamorphic optics required for 0.55-NA, the field size is reduced compared to traditional 0.33-NA scanners.

Standard EUV lithography allows for a 26 x 33 mm exposure field using 6-inch photomasks. In contrast, High-NA’s anamorphic 4X/8X magnification restricts the effective field to roughly 26 x 16.5 mm. For the massive, high-performance CPU and GPU dies of today, this creates a bottleneck. Engineers must "stitch" two separate exposures together to create a single, large chip.

The Drawbacks of the Stitching Methodology:

1. Reduced Throughput: Stitching requires double the exposure steps for a single die, dropping an EXE:5200B’s capacity from 175 wafers per hour to roughly 125.
2. Design Constraints: Floor planning becomes significantly more complex. Engineers must design chips with the "stitch line" in mind, limiting architectural freedom.
3. Yield Sensitivity: The alignment required for stitching is microscopic. Even minor deviations can result in broken interconnects or distorted lines, leading to potential defects. As chip complexity grows, the cost of these defects scales exponentially.

Intel’s Strategic Vision: The 6×12 Photomask

To move beyond the limitations of stitching, Intel has emerged as the primary advocate for a new industry standard: the 6×12-inch photomask. By doubling the length of the mask, the industry could theoretically achieve a 26 x 33 mm full-field exposure in a single pass, eliminating the need for stitching entirely.

However, the transition to a 6×12-inch format is not a simple hardware upgrade. It represents a massive, capital-intensive retooling of the entire semiconductor supply chain. Changes would be required for:

• Mask Blanks and Deposition: New material handling systems for larger, more fragile reticles.
• Inspection and Metrology: Current optical inspection tools are calibrated for the 6×6 footprint.
• Pellicles and Handling: The entire cleanroom robotics infrastructure would need to be redesigned to accommodate the larger, heavier masks.
• Scanner Redesign: While future scanners could be built to accommodate these masks, it remains an open question whether existing High-NA machines can be retrofitted.

Despite the monumental costs associated with this shift, Intel appears committed to the vision. By pushing for this standard, Intel is not just solving a technical problem; it is attempting to define the roadmap for the next two decades of lithography.

Implications for the Semiconductor Landscape

Intel’s achievement of the one-million-wafer milestone serves as a clear signal to the market: High-NA EUV is no longer a theoretical exercise—it is the engine of modern high-performance computing.

The First-Mover Advantage

By being the first to master High-NA at scale, Intel is positioning itself to lead the industry in cost-per-transistor efficiency. If Intel succeeds in ushering in the 6×12-inch mask era, they will effectively dictate the standard for the entire ecosystem. Peers who rely on stitching will face higher production costs and lower yields for large-die products, while Intel’s process flow will be optimized for full-field exposure.

A New Era of Competition

The race for process leadership has historically been a battle of nanometers. Today, it is a battle of ecosystem integration and operational scale. Intel’s ability to move from an early adopter to the dominant user of High-NA technology demonstrates a resurgence in its manufacturing capabilities.

As we look toward 2033 and beyond, the industry will undoubtedly continue to grapple with the laws of physics. However, with the million-wafer milestone in the rearview mirror, Intel has proven that the "High-NA era" is well underway. The question for the rest of the industry is no longer if they should adopt High-NA, but whether they can keep pace with the massive scale that Intel has established.

In the coming years, the transition to larger photomasks will likely become the next great battlefield. Whether the industry follows Intel’s lead or attempts to refine the current stitching paradigm remains to be seen. Regardless, the momentum generated by this latest milestone ensures that Intel will remain a central, if not dominant, force in the future of silicon fabrication.