China’s Semiconductor Ambitions: IMECAS Achieves GAA Transistor Milestone Amid EUV Restrictions

In a significant development for the global semiconductor landscape, the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) has successfully demonstrated functional stacked-nanosheet gate-all-around (GAA) transistors. The achievement, reported via DigiTimes, marks a critical pivot for Chinese domestic chipmakers. By utilizing existing immersion deep ultraviolet (DUV) lithography tools rather than the highly restricted extreme ultraviolet (EUV) scanners, researchers at IMECAS have laid a theoretical and practical foundation for building transistors at the 3nm-class node and beyond.

While the scientific community has greeted the news as a testament to Chinese engineering resilience, industry analysts urge caution. The transition from a laboratory-proven device to a high-yield, mass-production process is a chasm that few organizations have bridged without access to state-of-the-art lithography equipment.

The Core Achievement: Breaking the EUV Dependency

The transition from FinFET (Fin Field-Effect Transistor) to GAA (Gate-All-Around) architecture represents the most significant paradigm shift in semiconductor manufacturing in the last decade. As transistors shrink to the 3nm node and below, traditional FinFET structures suffer from severe short-channel effects and current leakage. GAA, or nanosheet, architecture solves this by wrapping the gate material around the channel on all sides, providing superior electrostatic control.

Historically, the industry consensus was that GAA manufacturing required EUV lithography to achieve the extreme precision necessary for stacking silicon nanosheets. However, the export controls imposed by the United States and its allies on advanced EUV scanners have effectively blocked Chinese firms like SMIC from accessing the machines produced by ASML.

IMECAS’s recent breakthrough demonstrates an experimental process flow that utilizes immersion DUV lithography—a technology that, while older, remains accessible to Chinese foundries. By optimizing multi-patterning techniques and sophisticated etching processes, the researchers have managed to fabricate functional GAA devices, proving that EUV is not strictly "impossible" to circumvent, even if the path forward remains fraught with technical and economic hurdles.

Chronology of China’s Semiconductor Pivot

To understand the significance of this development, one must examine the timeline of China’s push toward semiconductor self-sufficiency:

• 2019–2020: The Early Export Restrictions: The U.S. Department of Commerce tightened regulations on semiconductor manufacturing equipment, specifically targeting the sale of EUV machines to China. This effectively froze China’s ability to compete at the 7nm node and below using standard Western industry workflows.
• 2021–2022: The "Double Exposure" Era: Chinese foundries, led by SMIC, began experimenting with advanced multi-patterning using DUV systems to produce 7nm-class chips. While yield rates were initially reported as low, these efforts proved that DUV could be pushed far beyond its intended limitations.
• 2023: The 7nm Milestone: Huawei and SMIC shocked the industry by releasing the Kirin 9000S, a 7nm-class processor. This confirmed that China had successfully utilized DUV-based multi-patterning for mass production, despite the lack of EUV.
• September 2024 (Current Context): IMECAS announces the functional GAA nanosheet architecture. This signals that Chinese research institutions are already looking past the 7nm/5nm "DUV wall" and are preparing for the next generation of sub-3nm scaling.

Supporting Data and Technical Realities

Despite the excitement surrounding the announcement, the data currently available is limited. IMECAS has remained tight-lipped regarding the specific geometrical parameters of their GAA devices. In the semiconductor industry, "functional" is a broad term. To be comparable to 3nm offerings from TSMC, Samsung, or Intel, a transistor must meet specific metrics regarding gate pitch, nanosheet width, and electrical performance (Ion/Ioff ratios).

The "Process Flow" Limitation

It is crucial to distinguish between a "research flow" and a "manufacturing process." The IMECAS breakthrough is currently an experimental flow designed to demonstrate physical viability. A production process, by contrast, must account for:

1. Defect Density: Maintaining a yield high enough to make a multi-billion-dollar fab profitable.
2. Throughput: DUV multi-patterning requires significantly more mask layers and exposure steps than EUV, drastically increasing the time-per-wafer and cost-per-die.
3. Thermal Management: GAA structures present unique heat dissipation challenges that are compounded by the materials used in DUV-based fabrication.

While IMECAS has proved the concept, they have not yet disclosed whether their flow can be scaled to the complexity of a modern CPU or GPU, which consists of billions of these transistors working in concert.

Official Responses and Industry Outlook

The scientific and geopolitical community has reacted with a mix of admiration and skepticism.

The View from Domestic Chinese Industry:
Sources within the Chinese semiconductor ecosystem suggest that the IMECAS breakthrough is less about immediate commercial viability and more about "strategic insurance." By demonstrating that they can engineer GAA structures using DUV, Chinese researchers are providing local foundries with a roadmap for survival should EUV access remain restricted for the next decade.

The View from Global Analysts:
International observers, including firms like TrendForce and TechInsights, highlight the "economic cliff" that Chinese foundries face. An executive at a leading semiconductor firm, speaking on condition of anonymity, noted: "Demonstrating a functional GAA transistor in a lab is a phenomenal achievement in physics. But doing it at a cost that allows for consumer electronics parity is a different challenge entirely. You can use a hammer to drive a screw, but it isn’t an efficient way to build a house."

The prevailing consensus is that while China is closing the technological gap, the economic gap caused by the lack of EUV efficiency is widening.

Implications: A New Era of Semiconductor Fragmentation

The IMECAS breakthrough carries profound implications for the global tech industry:

1. The Fragmentation of Process Nodes

We are likely entering an era where there are two distinct "nodes" at every level. There will be the "Global/EUV node" (highly efficient, low cost, high yield) and the "Chinese/DUV node" (higher cost, lower yield, more complex manufacturing). This will lead to a bifurcated market where Chinese electronics may rely on domestic silicon that performs well but costs significantly more to produce.

2. The Acceleration of Domestic Tooling

The success of this GAA process will undoubtedly accelerate the state-funded push to develop indigenous Chinese lithography tools. If Chinese researchers can master the transistor architecture, the next logical step is to improve the quality of the DUV machines themselves, perhaps through improved computational lithography and novel phase-shift masks that mitigate the need for EUV.

3. Long-term Geopolitical Positioning

For Western policymakers, the IMECAS news is a signal that export controls have served as a catalyst for innovation rather than a permanent barrier. By forcing Chinese researchers to solve the GAA puzzle without EUV, the restrictions have inadvertently pushed them to develop more creative, albeit more expensive, manufacturing methodologies.

Conclusion

The Institute of Microelectronics of the Chinese Academy of Sciences has reached a high-water mark in semiconductor research. By proving that stacked-nanosheet GAA transistors can be built with existing DUV infrastructure, they have successfully debunked the myth that the path to 3nm is exclusively paved by EUV lithography.

However, the road ahead remains treacherous. The difference between a functional laboratory device and a commercial-grade 3nm processor is vast, requiring an ecosystem of equipment, materials, and yield-management techniques that China is still actively constructing. For the global semiconductor industry, this development serves as a stark reminder: in the race for technological sovereignty, necessity remains the most potent driver of invention. Whether this invention can be industrialized at scale remains the defining question of the next decade of silicon manufacturing.